This invention is in the field of semiconductor power devices. Disclosed embodiments are directed to termination regions for vertical power transistors, including metal-oxide-semiconductor superjunction transistors.
As known in the art, semiconductor power switching devices are ideally capable of blocking large forward and reverse voltages with minimal current conduction when in the “off” state while conducting large currents with minimal voltage drop when in the “on” state, with minimal switching times and minimal switching power consumption. Improvements in manufacturing yield and reduction in manufacturing cost are also sought. Advances toward these ideal attributes have largely been made in modern power transistors through innovations in device architecture, rather than through shrinking of device features sizes as in the case of low-power semiconductor devices such as digital logic and memory devices.
In this regard, vertical power devices are now widely used in many power applications. These devices are vertical in the sense that current is conducted vertically, through a drift region between the device surface and its substrate. The length of this drift region can absorb a large depletion region in the off-state and thus establish a high reverse breakdown voltage, which enables high voltage operation. Well-known types of vertical power devices include vertical drift metal-oxide-semiconductor (VDMOS) field-effect transistors, insulated gate bipolar transistors (IGBTs), and vertical power diodes, all of which include a drift region sufficient to support the desired high breakdown voltage. VDMOS devices have become particularly attractive because of their fast switching speeds, and as such are particularly well-suited for implementation into switched-mode power supplies. FIG. 1a illustrates, in cross-section, an example of the construction of a conventional VDMOS transistor, in the form of an n-channel MOS transistor. VDMOS 2 of FIG. 1a has its drain terminal at n+ substrate 4, and a drift region provided by n-type epitaxial layer 6, which overlies substrate 4 and extends to the surface of the device as shown. P-type body regions 8 at the surface of n-type epitaxial layer 6 serve as the VDMOS body region, within which one or more n+ regions 10 serve as the source of VDMOS 2. Gate dielectric 11 and gate electrode 12 overlie a portion of p-type body regions 8 between source region 10 and the drain at n-type epitaxial layer 6. Bias is supplied to VDMOS 2 by way of metal conductors 14 contacting n+ source regions 10 and p-type body regions 8 (typically at p+ contact regions formed within p-type body regions 8, not shown), so that the body region of VDMOS 2 is biased at the source potential. Other conductors (not shown) contact gate electrode 12 and substrate 4 to provide gate and drain bias, respectively. As in any n-channel MOS transistor, vertical power VDMOS 2 is biased into the on-state by a voltage at gate electrode 12 that exceeds the transistor threshold voltage under sufficient drain-to-source bias, which will be very high (e.g., as high as several hundred volts) in typical power applications. As shown in FIG. 1a, on-state source-drain current Ids conducts from source regions 10 laterally along an inversion layer in the body region of p-type body regions 8, and vertically through epitaxial layer 6 into substrate 4 at the transistor drain. The on-resistance of VDMOS 2 includes the channel resistance Rch in p-type body regions 8, but is typically dominated by the resistance Repi of n-type epitaxial layer 6 because of the thickness and relatively light dopant concentration of that layer. While an increase in the doping concentration of epitaxial layer 6 would reduce resistance Repi and thus reduce the overall on-resistance of VDMOS 2, typical VDMOS devices must withstand high drain-to-source voltages (e.g., on the order of hundreds of volts) in the off-state. Because the breakdown voltage of VDMOS 2 is directly related to the thickness of its n-type epitaxial layer 6 (i.e., the VDMOS “drift” length), and is inversely related to the dopant concentration of the more lightly-doped epitaxial layer 6, this structure presents a tradeoff between on-resistance and off-state breakdown voltage.
Also as known in the art, “superjunction” VDMOS transistors address this tradeoff. FIG. 1b illustrates an example of such a conventional superjunction VDMOS 2′, also for the case of an n-channel device. Superjunction VDMOS 2′ is constructed similarly as non-superjunction VDMOS 2 of FIG. 1a insofar as the surface structures (p-type body regions 8, n+ source regions 10, gate electrode 12, etc.) are concerned. However, in contrast to the non-superjunction VDMOS 2 of FIG. 1a, the epitaxial region of superjunction VDMOS 2′ is filled with p-type doped “pillars” 9 formed into epitaxial layer 6′. These p-type pillars 9 may be constructed by ion implantation during the formation of epitaxial layer 6′ silicon, for example in a multiple step epitaxial process in which a p-type pillar implant is performed after epitaxy of a portion of layer 6′, such that each pillar 9 is formed as a number of vertically aligned segments. P-type body regions 8 and n+ source regions 10 are typically self-aligned with gate electrode 12, with p-type body regions 8 typically implanted prior to the n+ source implant, and receiving a dedicated drive-in anneal, so as to extend farther under gate electrode 12 than its corresponding n+ source region 10, with p-type body regions 8 typically extending slightly into the surface region of the n-type epitaxial region. The dopant concentration of p-type body regions 8 is optimized for the desired MOSFET characteristics, such as threshold voltage and punch-through, while the dopant concentration of p-type pillars 9 is optimized for charge balance in the off-state, and will typically be more lightly doped than body regions 8. In the on-state, VDMOS 2′ conducts source-drain current Ids in the same manner as described above for non-superjunction VDMOS 2, in this case with current conducted through the n-type drift regions presented by the portions of n-type epitaxial layer 6′ between p-type pillars 9. In the off-state, however, p-type pillars 9 and the n-type drift regions of epitaxial layer 6′ will essentially fully deplete under the typical high drain-to-source voltage, that is, because of the additional p-type material presented deep into the structure by pillars 9, a corresponding amount of charge will also deplete from n-type epitaxial layer 6′ to attain charge balance. This additional charge cancellation in the off-state resulting from pillars 9 according to this superjunction construction enables epitaxial layer 6′ to have a higher dopant concentration, and thus a lower on-state resistance Repi, without adversely affecting the breakdown voltage in the off-state.
FIG. 1c illustrates the construction of a conventional trench gate superjunction VDMOS device. In this example, gate electrode 12′ of VDMOS transistor 2″ is disposed within a trench etched into the surface of the device, insulated from the surrounding semiconductor by gate dielectric 11′. The channel region of VDMOS 2″ in body region 8 is thus oriented vertically, adjacent to gate dielectric 11′ and gate electrode 12′. Pillars 9 extend below body region 8′ to provide charge cancellation for VDMOS 2″ in the off-state as described above.
As also known in the art, in order to support the high currents required of the intended application, VDMOS transistors are typically constructed as multiple parallel-connected source and body regions, and corresponding gate electrodes, typically arranged in “stripes” or as an array of cells within the “core” or active region of the device (i.e., that region of the integrated circuit die that passes source-drain current in the on-state). In the off-state, the top surface of the core region will be at or near the gate and source voltage, at ground potential, while the substrate will be at or near the applied drain voltage. An electric field in this core region will be oriented vertically from the fully depleted core region to the substrate, and must remain below the critical electric field for the semiconductor at which avalanche begins, typically about 3×107 V/m for silicon.
In this construction, however, the top outer edge of the integrated circuit device will also be at or near the voltage applied to the substrate (i.e., the drain terminal). In the off-state, a lateral electric field, parallel to the surface of the device, will thus also be present between the core region and the perimeter of the device. In order to avoid junction breakdown in this lateral direction, conventional VDMOS devices typically include a termination region surrounding the core region to laterally sustain the off-state drain-to-source voltage. Functionally, this termination region is intended to smoothly twist the electric field from vertical (at the core) to horizontal (at the outer edge of the die) while preventing the peak electric field from reaching the critical electric field.
Conventionally, the width of the termination region will be made of sufficient size (width) to lower the electric fields simply by increasing the distance over which the voltage gradient extends, thus avoiding breakdown within the termination region by maintaining the electric field magnitude below the critical electric field. By ensuring that the termination region breakdown voltage is sufficiently high, the device breakdown performance will be dominated by the larger core region of the device, allowing energy to be dissipated over a larger area and preventing localized heating that could lead to device destruction. However, the termination region does not add to on-state drive current, and therefore the chip area consumed to provide the termination region is essentially “overhead” from the standpoint of current delivered per unit of chip area. Minimization of the termination region area while still providing excellent breakdown characteristics, including both high breakdown voltage and low off-state current, is therefore desirable.
By way of further background, the use of field plates to set surface potentials to control the depletion region boundaries in such structures as vertical power diodes and power transistors is known. As known in the art, field plates refer to conductor or semiconductor structures at or near the surface of the power device that provide equipotential surfaces outside of the core region; these field plates may be biased to a desired potential, or may be left electrically floating. These equipotential surfaces alter the shape of the depletion layer in the underlying semiconductor, which redirect the electric field lines and increase the radius of curvature of the depletion layer boundary, thus increasing the breakdown voltage of the device. Guard rings, in the form of doped regions of opposite conductivity type within the semiconductor are also known in the art for similarly controlling the radius of curvature of the depletion layer boundary. In structures that present the possibility of a parasitic thyristor (i.e., a p-n-p-n structure), these guard rings are tied to an appropriate bias voltage to prevent triggering of that thyristor and latchup of the device.